(1) Field of the Invention
The present invention relates to a distortion compensating apparatus and a distortion compensating method. The invention relates particularly to an art suitable for use in a predistortion amplifier which compensates for nonlinearity of an amplifier by adaptively updating a distortion compensation coefficient for an input signal input to the amplifier based on a difference between input and output signals.
(2) Description of the Related Art
FIG. 7 is a block diagram showing a construction of an important part of a previous Digital Predistortion (DPD) amplifier. The DPD amplifier of FIG. 7 includes: a Lookup Table (LUT: a distortion compensation table) 110; an address generator 111; an LMS arithmetic operator (distortion compensation arithmetic operation unit) 112; a multiplier 113; an equalizer filter (complex filter) 114; a digital/analogue (D/A) converter 115; a Quadrature Modulating unit (QMOD) 116; a local oscillator 117; an amplifier 118; a directional coupler 119; a mixer (multiplier) 120; a local oscillator 121; an analogue/digital (A/D) converter 122; a 1/M clock (CLK)-unit delay circuit 123; a clock (CLK)-unit delay circuit 124; and a subtracter 125; an FFT arithmetic operator 126; an integrator 127; a bus 128; and a CPU 129.
In the DPD amplifier with such a construction, a complex signal X(I, Q), composed of an I signal and a Q signal, is input as an input signal (digital signal). The multiplier 113 multiplies the complex signal X(I, Q) by a distortion compensation coefficient given by the distortion compensation table 110, thereby performing distortion compensation, and the complex signal X(I, Q) is input to the equalizer filter 114. In this instance, the above complex signal X(I, Q) is also input to the address generator 111, which generates an index address for distortion compensation table 110, and the clock (CLK)-unit delay circuit 124, as a reference signal, respectively.
The equalizer filter 114 controls its internal parameter (filter coefficient) to perform inverse characteristic filtering of the frequency characteristic of the input signal X(I, Q) as schematically shown in FIG. 8, so that the phases of the reference signal X(I, Q) and a feedback signal Y(I, Q) of an output of the amplifier 118, which are input to the LMS arithmetic operator 112, do not have frequency components. As a result, a linear inclination frequency characteristic of an analogue circuit is compensated for. In this instance, in FIG. 8, the input signal X(I, Q) is a multi carrier signal including four carriers of C1, C2, C3, and C4. FIG. 8 shows that the above-described filtering is capable of compensating for the frequency deviation of the power values of the carriers C1 through C4.
With this arrangement, the phase relationship of each carrier signal component (C1, C2, C3, and C4) on the frequency axis between the reference signal X(I, Q) and the feedback signal Y(I, Q) becomes constant, the DPD operation ability being thereby improved. In this instance, although FIG. 7 does not illustrate it, the equalizer filter 114 is connected to the CPU 129 via the bus 128, and the above-mentioned filter coefficient is controlled by the CPU 129.
The signal, whose frequency characteristic is compensated for by the equalizer filter 114 as described above, is converted into an analogue signal by the D/A converter 115, and is then modulated (quadrature modulation) by the quadrature modulating unit 116 based on an output of the local oscillator 117, and is input to the amplifier 118 as a signal in a radio frequency (RF) band. The input signal is amplified by the amplifier 118 up to a required power value (transmission power value), and is then output.
A part of the output signal is split by the directional coupler 119, and is fedback to the mixer 120, which multiplies the split signal by an output of the local oscillator 121, thereby demodulating (quadrature detection) the signal. The demodulated signal is output as a signal in an IF band, and is then converted into a digital signal (complex signal) Y(I, Q) by the A/D converter 122. After that, the signal is input to the 1/M clock (CLK)-unit delay circuit 123, the FFT arithmetic operator 126, and the integrator 127, respectively.
As schematically shown in FIG. 9, for example, the 1/M clock-unit delay circuit (digital filter) 123 delays the feedback signal Y(I, Q) so that the above feedback signal Y(I, Q) and the reference signal X(I, Q) are input to the subtractor 125 at the same timing. For this purpose, the 1/M clock-unit delay circuit 123 is capable of delaying the feedback signal Y(I, Q) with an accuracy of 1/M clock, by controlling its internal parameter [a filter (tap) coefficient of a delay filter tap from 0 to (M−1): M is an arbitrary number]. The 1/M clock-unit delay circuit 123 delays the feedback signal Y(I, Q) by a desired time Δt in 1/M clock units, and inputs the delayed signal Y (I, Q) to the subtractor 125. The reference signal X(I, Q) is delayed by the clock-unit delay circuit 124 in clock units, and is then input to the subtractor 125.
That is, to realize comparison of signals of the same time by the subtracter 125, these delay circuits 123 and 124 separately delay the reference signal X(I(t−n), Q(t−n)) and the feedback signal Y(I(t−Δt), Q(t−Δt)), which are deviated in a time relationship, to make the two signals match on the time axis with good accuracy. At that time, the delay amount Δt (fine adjustment), which is smaller than a clock frequency, is delayed by the digital filter 123. In this instance, this digital filter 123 is also connected to the CPU 129 via the bus 128, and the CPU 129 controls the internal parameter (filter coefficient) of the digital filter 123, thereby controlling a delay amount.
Then, the subtracter 125 performs subtraction processing on the signals X (I, Q) and Y (I, Q) of the same time, whose input timings are matched due to the above delay adjustment, thereby detecting an error signal. On the basis of the error signal, the distortion compensation arithmetic operator 112 updates distortion compensation coefficients in the distortion compensation table 110 using, for example, the LMS algorithm.
As described above, the DPD amplifier adaptively updates a distortion compensation coefficient used in distortion compensation (multiplier 113) of the input signal X (I, Q) based on a difference (error) between the reference signal X(I, Q) and the feedback signal Y(I, Q), and compensates for nonlinear distortion of the amplifier 118, thereby improving the amplification efficiency.
Here, internal parameters (filter coefficients) of the equalizer filter 114 and the digital filter 123 are adaptively corrected by the CPU 129. That is, the FFT arithmetic operator 126 performs FFT processing on the feedback signal Y(I, Q), thereby performing frequency analysis. From the result (FFT result data), the CPU 129 obtains data equivalent to ACLR (Adjacent Channel Leakage Ratio) 5 MHz carrier separation under the 3GPP standards.
For example, in a case where data (data of frequency vs. power value) shown in FIG. 11 is obtained as the FFT result data, the CPU 129 obtains data of measurement points (monitoring range) indicated by the frames 100 whose center frequency is apart from the center frequency of the power value obtaining points indicated by the frames 200 by 5 MHz in the central direction. In this instance, in FIG. 11, the power value obtaining points 200 indicate ranges of power values obtained by an integration operation by the integrator 127; C1, C2, C3, and C4 designate carrier signal components already described.
As schematically shown in FIG. 10, of the data obtained at the above-mentioned measurement points 100, the CPU 129 compares high-frequency data with low-frequency data, and regards the worse data (data with a greater distortion deterioration amount within the monitoring range) as distortion data. The CPU 129 obtains the distortion data while changing the above-mentioned parameters, and corrects the parameters so that the distortion data is improved. Here, with the construction shown in FIG. 7, the distortion amount is not only changed by changing the parameters, and the distortion amount difference becomes definite by updating distortion compensation coefficients in the distortion compensation table 110.
In this instance, the integrator 127 integrates the feedback signal Y(I, Q), and notifies the CPU 129 of the power value (the power value obtained at the power value obtaining points 200 in FIG. 11) via the bus 128, thereby making it possible for the CPU 129 to detect abnormal transmission power and to output an alarm.
As a previous DPD art, there is an art proposed in the following patent document 1.
The object of the art in patent document 1 is to provide a linear power amplifier and a linear power amplification method which are low in change over time and in change due to temperature and which is high in distortion amount. The art in patent document 1 also intends to provide a method for setting of a digital pre-distorter. To realize the above objects, the DPD generates a predistortion-added signal to which odd number order distortion due to power series model is given, and extracts, from an amplifier output, an odd number order distortion component of the power series model from a pilot signal component.
That is, a pilot signal component is extracted from the output of the power amplifier, and odd number order distortion of power series model of the digital pre-distorter is directly feedback controlled, so that the level of the odd number order distortion component extracted from the pilot signal component becomes small. As a result, it is possible to provide a linear power amplifier with small changes over time and small changes due to temperature. The odd number order distortion is compensated for by the inverse characteristics of the frequency characteristics of the power amplifier, so that distortion of the power amplifier can be removed across a wide band.
[Patent Document1] Japanese Patent Application Laid-open No. 2005-65211
However, in cases where the amplifier distortion is great before distortion compensation, the distortion compensation cannot sufficiently work. For this reason, it is sometimes impossible to satisfy the radio characteristics as a transmitter simply by obtaining data equivalent to ACLR 5 MHz carrier separation. For example, as shown in FIG. 12, even if the specification of ACLR 5 MHz carrier separation of 3GPP can be satisfied, more stricter specification at more distant frequency falls outside the ACLR 10 MHz carrier separation specification.
That is, it is insufficient to obtain data equivalent to ACLR 5 MHz carrier separation as a parameter correction operation, and distortion data measurement at an appropriate point (frequency) meeting the ACLR specification is necessary. In this instance, the above patent document 1 does not disclose or suggest that setting of an appropriate distortion data measuring point in accordance with the ACLR specification is necessary.